Method for dicing semiconductor wafer into chips

ABSTRACT

A method for dividing a semiconductor wafer into chips according to the present invention is a method for dividing a semiconductor wafer into a large number of semiconductor chips, the semiconductor wafer having a semiconductor layer formed on a substrate. A first method includes the step of forming a blast-resistant mask on a surface of the semiconductor wafer, the blast-resistant mask having a pattern for leaving a grid-like exposed portion as it is and the step of blasting a fine particular blast material to thereby form dividing grooves reaching a predetermined depth of the substrate in the grid-like exposed portion. A second method includes the step of forming first dividing grooves in a surface of the semiconductor wafer in which the semiconductor layer is formed, by dicing, etching or blasting, so that the first dividing grooves have a relatively narrow groove width, and the step of forming second dividing grooves in a surface of the semiconductor wafer in which the semiconductor layer is not formed by dicing, and in positions corresponding to the first dividing grooves, so that the second dividing grooves have a relatively wide groove width.

TECHNICAL FIELD

The present invention relates to a method in which a semiconductor waferhaving a semiconductor layer formed on a substrate is divided into alarge number of semiconductor chips.

BACKGROUND ART

As a method for dividing a semiconductor wafer, there is generallyadopted a method in which grooves are formed in the wafer by dicing orscribe lines are formed by scribing, and the wafer is then divided bybreaking with the aforementioned grooves or the scribe lines as startingpoints and along the scribe lines. Dicing is a method for forming dicinggrooves in the wafer by the relative movement between a rotary blade ofa dicer (dicing saw) and the wafer. Scribing is a method for formingscribe lines in the wafer by the relative movement between a sharp-edgedblade of a scriber and the wafer. Breaking is a method for pressing thewafer with a press blade or a press roller to thereby divide the waferby three-point bending.

In a semiconductor wafer using a substrate made of a high-hardnessmaterial (e.g. sapphire, GaN, etc.), it is difficult to divide the waferby breaking only if shallow dicing grooves or scribe lines are formed inthe wafer. It is therefore necessary to do breaking after ingenuity suchas dicing the wafer deep, scribing the wafer with the substrate thinnedon a large scale, or the like, is added. For example, the followingmethods are known as methods in which a wafer having agallium-nitride-based compound semiconductor laminated onto the surfaceof a sapphire substrate is divided into chips.

(1) A method disclosed in Japanese Patent No. 2765644 includes thefollowing steps:

-   1) the dicing step of cutting grooves deeper than the thickness of    the gallium-nitride-based compound semiconductor layer by a dicer;-   2) the grinding step of thinning the sapphire substrate by grinding;-   3) the scribing step of forming scribe lines in the sapphire    substrate with a scriber along the grooves formed in the dicing    step; and-   4) the dividing step of dividing the wafer into chips after the    scribing step.    (2) A method disclosed in Japanese Patent No. 2914014 includes the    following steps:-   1) the first step of thinning the sapphire substrate by grinding;-   2) the second step of etching a p-type layer (gallium-nitride-based    compound semiconductor) up to an n-type layer to thereby expose the    plane of the n-type layer;-   3) the third step of etching or dicing the plane of the n-type layer    to thereby expose the plane of the sapphire substrate; and-   4) the fourth step of dicing or scribing the thinned sapphire    substrate, and cutting off the wafer in the plane of the sapphire    substrate exposed in the third step.    (3) A method disclosed in Japanese Patent No. 2780618 includes the    following steps:-   1) the step of forming first split grooves linearly into the shape    of desired chips by etching on the side of the gallium-nitride-based    compound semiconductor layer, while forming a plane in a part of the    first split grooves so that electrodes can be formed in the plane;-   2) the step of forming second split grooves (preferably scribe    lines) in the positions corresponding to the first split grooves on    the side of the sapphire substrate of the wafer so that the line    width of the second split grooves is narrower than the line width of    the first split grooves; and-   3) the step of dividing the wafer into chips along the first split    grooves and the second split grooves.    (4) A method disclosed in Japanese Patent No. 2861991 includes the    following steps:-   1) the step of forming (by etching) first split grooves linearly    into the shape of desired chips on the side of the    gallium-nitride-based compound semiconductor layer of the wafer,    while forming the first split grooves to reach a depth to an extent    that the gallium-nitride-based compound semiconductor layer is    penetrated and a part of the sapphire substrate is removed;-   2) the step of forming second split grooves (preferably scribe    lines) in the positions corresponding to the first split grooves on    the side of the sapphire substrate of the wafer so that the line    width of the second split grooves is narrower than the line width of    the first split grooves; and-   3) the step of dividing the wafer into chips along the first split    grooves and the second split grooves.

In the methods using dicing and scribing together as in theaforementioned (1) and (2), first, there is a problem that cracking orchipping is apt to occur in the substrate and the semiconductor layer atthe time of dicing so that the yield is not very high. In addition, itis necessary to form a large number of dicing grooves and a large numberof scribe lines in the wafer. In the present circumstances, those lineshave to be formed one by one. Thus, the machining time is so long thatthe efficiency deteriorates. Further, a rotary blade for dicing isexpensive and does not have a very long lifetime.

Further, in the method in which grooves are formed by dicing on thesemiconductor layer formation side so as to reach the substrate, andscribe lines are formed in the bottoms of the grooves by a scriber as inthe aforementioned (1), the groove width of the grooves has to be madeso large that a scribing blade enters the grooves.

On the other hand, in the methods using etching and scribing together asin the aforementioned (3) and (4), first, there is a fear that etchingcauses damage to the semiconductor layer. Japanese Patent No. 2780618 asin the aforementioned (3) says “Etching is the least efficient way tocause damage to the surface and side faces of the nitride semiconductor”and takes, for instance, dry etching such as reactive ion etching, ionmilling, converging beam etching, ECR etching, etc., and wet etchingusing mixed acid of sulfuric acid and phosphoric acid. Such etching canindeed form a plurality of or a large number of grooves simultaneously,but the machining time is not short at all, so that the efficiency ispoor. Further, equipment for etching, particularly equipment for dryetching is so expensive that the machining cost increases.

Further, the reason why the line width of the first split grooves on thesemiconductor layer formation side is made larger than the line width ofthe second split grooves on the sapphire substrate side as in theaforementioned (3) and (4) is to prevent any cutting line generated inthe second split grooves from reaching the semiconductor layer even ifthe line runs obliquely. Accordingly, in embodiments of the sameapplications, the line width of the first split grooves is made wide tobe 80 μm. When the groove width of the grooves formed thus on thesemiconductor layer formation side is made wide, there is a problem thatthe area of the semiconductor layer in each semiconductor chip dividedis reduced so that the luminance becomes low. In addition, when the areais prevented from being reduced, there is a problem that the number ofsemiconductor chips yielded is reduced.

DISCLOSURE OF THE INVENTION

A first object of the present invention is to provide a method fordividing a semiconductor wafer into chips, in which the foregoingproblems are solved, the yield is excellent, the efficiency is high, andthe equipment cost and the machining cost can be reduced.

A second object of the present invention is to provide a method fordividing a semiconductor wafer into chips, in which the foregoingproblems are solved, the area of a semiconductor layer in eachsemiconductor chip divided is increased so that the luminance can beenhanced or the number of semiconductor chips yielded can be increased,while breaking can be facilitated.

From the first point of view, the present invention provides a methodfor dividing a semiconductor wafer into a large number of semiconductorchips, the semiconductor wafer having a semiconductor layer formed on asubstrate, including the step of forming a blast-resistant mask on asurface of the aforementioned semiconductor wafer, the blast-resistantmask having a pattern for leaving a grid-like exposed portion as it isand the step of blasting a fine particle blast material to theaforementioned semiconductor wafer to thereby form dividing groovesreaching a predetermined depth of the aforementioned substrate in theaforementioned grid-like exposed portion.

Here, it is preferable that the blasting is carried out by blasting thefine particle blast material so as to spread the fine particle blastmaterial over a plurality of grid lines of the grid-like exposed portionwhile feeding the semiconductor wafer and a blasting machine such as anozzle relatively to each other in the plane direction of thesemiconductor wafer, so that a plurality of dividing grooves are formedsimultaneously. This arrangement is made so that the dividing groovesare accurate to be dug in the widthwise direction of the semiconductorwafer, and the efficiency of forming the dividing grooves is enhanced.

In this case, the distance between the semiconductor wafer and thenozzle is not limited particularly, but is preferably 10-150 m. When thedistance is too small, damage to the mask increases. When the distanceis too large, the machining speed becomes so low that the machining timebecomes long.

In addition, the feeding speed is not limited particularly, but ispreferably 5-200 mm/sec. When the feeding speed is too low, damage tothe mask increases due to heating or the like. When the feeding speed istoo high, the degree of verticality in rising faces of machined portionsdeteriorates.

In addition, the aforementioned blasting while feeding may be repeated apredetermined pass number of times so that the depth of the dividinggrooves can be increased. This pass number of times is not limitedparticularly, but is preferably 3-20 passes.

The width of the dividing grooves is not limited particularly, but ispreferably 10-500 μm. When this width is too small, not only is itpossible to obtain a sufficient depth but it also becomes difficult toselect the fine particle blast material. When this width is too large,the number of semiconductor chips yielded is reduced.

The depth of the dividing grooves in the substrate is not limitedparticularly, but is preferably 1-100 μm, more preferably 5-50 μm. Whenthis depth is too small, the operation to reduce the thickness of thesubstrate remaining under the grooves to thereby facilitate the divisionof the wafer becomes weak. When this depth is too large, it takes muchtime for blasting.

The material of the fine particle blast material is not limitedparticularly. However, when the substrate is made of sapphire or GaN, itis preferable that the fine particle blast material is made of amaterial having a Vickers hardness of at least 120. Specifically, forexample, the fine particle blast material is preferably at least onekind selected from alumina, silicon carbide, boron nitride, boroncarbide and diamond.

The average particle size of the fine particle blast material is notlimited particularly if it is smaller than the width of the dividinggrooves. However, the average particle size of the fine particle blastmaterial is preferably ½- 1/20 by representation using a ratio to thewidth of the dividing grooves or preferably 1-30 μm by representationusing a numeric value, and more preferably 5-15 μm. When this averageparticle size is too small, the kinetic energy becomes small. When thisaverage particle size is too large, the smoothness of the dividinggrooves is degraded.

The blast rate of the fine particle blast material is not limitedparticularly, but is preferably 30-100 g/sec. When the blast rate is toolow, the machining speed becomes low. When the blast rate is too high,the damage to the mask increases.

The blast pressure of the fine particle blast material is not limitedparticularly, but is preferably 0.2-0.8 MPa. When the blast pressure istoo low, the machining speed becomes low. When the blast pressure is toohigh, damage to the mask increases.

The dividing grooves may be formed in the surface of the semiconductorwafer in which the semiconductor layer is formed, or may be formed inthe surface of the semiconductor wafer in which the semiconductor layeris not formed. Alternatively, the dividing grooves may be formed in boththe surfaces of the semiconductor wafer.

In addition to the aforementioned steps, the method according to thepresent invention may include the step of forming scribe lines byscribing the groove bottoms of the dividing grooves or the surface ofthe semiconductor wafer opposite to the dividing grooves, and mayfurther include the step of dividing the semiconductor wafer intosemiconductor chips by breaking with the scribe lines as startingpoints.

Further, from the second point of view, the present invention provides amethod for dividing a semiconductor wafer into a large number ofsemiconductor chips, the semiconductor wafer having a semiconductorlayer formed on a substrate, including the step of forming firstdividing grooves in the surface of the semiconductor wafer in which thesemiconductor layer is formed, by dicing, etching or blasting, so thatthe first dividing grooves have a relatively narrow groove width, andthe step of forming second dividing grooves in the surface of thesemiconductor wafer in which the semiconductor layer is not formed, andin positions corresponding to the first dividing grooves, so that thesecond dividing grooves have a relatively wide groove width. Not to say,the words “relatively narrow or wide” are mentioned about the relativerelationship between the groove width of the first dividing grooves andthe groove width of the second dividing grooves.

Here, as the “dicing”, there may be adopted a usual method for dicingwith a rotary blade to which diamond abrasive grains have adhered.

As the “etching”, there can be taken, for instance, dry etching such asreactive ion etching, ion milling, converging beam etching, ECR etching,etc., wet etching using mixed acid of sulfuric acid and phosphoric acid,and so on. Before the etching, an etching-resistant mask having apattern for leaving a grid-like exposed portion as it is, is formed inthe surface of the semiconductor wafer.

As the “blasting”, blasting similar to the aforementioned one may beadopted.

The method may further include the step of forming third dividinggrooves in the groove bottoms of the second dividing grooves by dicingso as to establish a relationship that groove width of the firstdividing grooves is not larger than groove width of the third dividinggrooves, and groove width of the third dividing groove is smaller thangroove width of the second dividing grooves.

The groove sectional shape of the second dividing grooves may be made asubstantially U-shape or a substantially V-shape which is the deepest inthe widthwise central portion thereof.

The groove width of the first dividing grooves is preferably 10-50 μm,more preferably 20-40 μm, (as long as it satisfies the aforementionedrelative relationship). When the groove width is small, it is differentto form the first dividing grooves. When the groove width is large, thearea of the semiconductor layer or the number of the semiconductor chipsyielded is reduced remarkably.

The groove width of the second dividing grooves is preferably 15-100 μm,more preferably 20-50 μm, (as long as it satisfies the aforementionedrelative relationship). When this groove width is small, the lifetime ofthe rotary blade of the dicer becomes short (there is a tendency thatthe thinner the rotary blade is, the shorter its lifetime is). When thisgroove width is large, the bottom area of the substrate in eachsemiconductor chip becomes so small that its mechanical stabilitydeteriorates.

The depth of the first dividing grooves and the depth of the seconddividing grooves are not limited particularly. However, it is preferablethat the first dividing grooves have a relatively small depth while thesecond dividing grooves have a relatively large depth. Since the groovewidth of the first. dividing grooves is relatively narrow, a thin rotaryblade having a tendency to have a short lifetime is used as the rotaryblade of the dicer for the first dividing grooves. It is thereforepreferable that the first dividing grooves are not made very deep. Onthe other hand, since the groove width of the second dividing grooves isrelatively wide, a thick rotary blade having a tendency to have a longlifetime is used as the rotary blade of the dicer for the seconddividing grooves. It is therefore easy to make the second dividinggrooves deep.

Then, the thickness of residual portions of the substrate remainingbetween the first dividing grooves and the second dividing grooves aremade preferably 20-100 μm, more preferably 20-50 μm. According to thepresent invention, breaking can be facilitated because the dividinggrooves are formed in both the surface of the semiconductor wafer inwhich the semiconductor layer is formed and the surface of thesemiconductor wafer in which the semiconductor layer is not formed. Byadjusting the thickness of the residual portions to be within theaforementioned range, the breaking can be made most easy.

Further, the second dividing grooves or the third dividing grooves maybe formed by dicing so as to reach the first dividing grooves. As aresult, the semiconductor wafer can be divided into semiconductor chipsdirectly without producing the aforementioned residual portions. Thatis, it is possible to omit the step of dividing the semiconductor waferinto semiconductor chips by breaking with the residual portions asstarting points.

The present invention from the aforementioned first and second points ofview is not limited by the material forming the substrate. However, thepresent invention is particularly effective when the substrate is madeof a high hardness material having a Mohs hardness of at least 8. Forexample, the present invention is particularly effective in dividing asemiconductor wafer whose substrate is made of sapphire or GaN, andwhose semiconductor layer is made of a gallium-nitride-based compoundsemiconductor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A and FIG. 1B are perspective views showing a method for dividinga semiconductor wafer into chips according to a first embodiment of thepresent invention;

FIG. 2A to FIG. 2C are sectional views showing the first half of thesteps of the same chip-dividing method;

FIG. 3A to FIG. 3C are sectional views showing the second half of thesteps of the same chip-dividing method;

FIG. 4A to FIG. 4F are sectional views showing examples of the samechip-dividing method;

FIG. 5A is a sectional view of a semiconductor wafer to be divided in amethod for dividing a semiconductor wafer into chips according to asecond embodiment of the present invention, and FIG. 5B is a plan viewwhen dividing grooves have been formed in the semiconductor wafer;

FIG. 6A to FIG. 6D are sectional views showing the chip-dividing methodaccording to the second embodiment;

FIG. 7A is a sectional view showing the main point of a chip-dividingmethod according to a third embodiment, FIG. 7B is a sectional viewshowing the main point of a chip-dividing method according to a fourthembodiment, and FIG. 7C is a sectional view showing the main point of achip-dividing method according to a fifth embodiment; and

FIG. 8A to FIG. 8C are sectional views showing the main point of achip-dividing method in which second dividing grooves or third dividinggrooves are formed by dicing so as to reach first dividing grooves inthe respective chip-dividing methods according to the third embodimentto the fifth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 to FIG. 3 shows a method for dividing a semiconductor wafer intochips according to a first embodiment of the present invention. First,description will be made on a semiconductor wafer 1 to be divided. Thesame wafer 1 is constituted by a substrate 2 and a semiconductor layer3. The semiconductor layer 3 is formed on the surface of the substrate 2so as to arrange a light emitting device (a light emitting diode, alaser diode, or the like). The same layer 3 is constituted by mainlayers 11 to 16 and electrodes (not shown).

The substrate 2 is made of sapphire, which is, for example, 2 inches(about 5 cm) square in the planar shape and 350 μm thick, and has ana-plane {11-20} in the surface on which the semiconductor layer will beformed. Incidentally, the substrate is not limited to this, but thematerial (for example, a substrate made of GaN may be used, and so on),the planar shape, the thickness, the crystalline plane, and so on may bechanged appropriately.

Each of the main layers 11 to 16 is a gallium-nitride-based compoundsemiconductor (a buffer layer is made of AlN, but may be made of GaN)formed in a metallorganic vapor phase epitaxy method. First, the AlNbuffer layer 11 is formed on the substrate 2. The Si-doped n-type GaNcontact layer 12 is formed on the layer 11. The n-type GaN clad layer 13is formed on the layer 12. The light emitting layer 14 having a multiplequantum well structure in which GaN barrier layers and InGaN well layershave been laminated alternately is formed on the layer 13. The Mg-dopedp-type AlGaN clad layer 15 is formed on the layer 14. The Mg-dopedp-type GaN contact layer 16 is formed on the layer 15. The totalthickness of the main layers 11 to 16 is not limited particularly, butis, for example, 2-15 μm.

Incidentally, the main layers are not limited to this configuration.Suitable modifications may be made as follows. That is, the compositionsof the respective layers may be changed. For example, the light emittinglayer may be changed to have a single quantum well structure. When thesubstrate 2 is made of GaN, the buffer layer 11 may be omitted. In thecase of a laser diode, a resonant structure may be provided.

Now, this semiconductor wafer 1 is divided into a large number ofsemiconductor chips in the following steps.

(1) As shown in FIG. 1A and FIG. 2A, a blast-resistant mask 5 having apattern for leaving a grid-like exposed portion 6 as it is, is formed onthe surface of the semiconductor wafer 1, for example, in which thesemiconductor layer is formed. The method for forming theblast-resistant mask 5 is not limited particularly, but photolithographyis adopted here. That is, a film with a photosensitive resist agent(masking agent) is pasted onto the semiconductor wafer 1, exposed toultraviolet rays, developed with a weak alkaline solution, and dried.Thus, the blast-resistant mask 5 having the aforementioned patternadheres onto the semiconductor wafer 1.

Each chip to be divided is about 350 μm square in the planar shape.Accordingly, the pitch between adjacent grid lines of the grid-likeexposed portion 6 is 350 μm both in the x-direction and in they-direction (see FIG. 1A and FIG. 1B). On the other hand, the dividinggrooves 7 to be formed are about 20, 30, 40 or 50 μm wide. Accordingly,the respective grid lines of the grid-like exposed portion 6 are about20, 30, 40 or 50 μm wide.

(2) This semiconductor wafer 1 is supported on a table (not shown) whichcan move in the x-y direction. While this table is moved to feed thesemiconductor wafer 1 in the x-y direction which is the plane directionof the semiconductor wafer 1, a fine particle blast material 21 isblasted on the semiconductor wafer 1 from a nozzle 20 of a blastingmachine so as to be spread over a plurality of grid lines of thegrid-like exposed portion 6 as shown in FIG. 2A. Thus, a plurality ofdividing grooves 7 are formed in the grid-like exposed portion 6simultaneously so as to reach a predetermined depth of the substrate 2.This formation is done by the operation that the kinetic energy of thefine particle blast material 21 blasted at a high speed shaves parts ofthe semiconductor layer 3 and the substrate 2 appearing in the grid-likeexposed portion 6 microscopically.

The distance between the semiconductor wafer 1 and the nozzle 20 is setto be about 50 mm. The feeding speed is set to be 50 mm/sec. Thematerial of the fine particle blast material is set to be siliconcarbide, and the average particle size thereof is set to be 8 μm (#2000meshes) or 13 μm (#1200 meshes). The blasting rate is set to be 60-90g/sec, and the blasting pressure is set to be about 0.4 MPa.

When one pass of blasting is carried out while feeding the semiconductorwafer 1 in such a manner, dividing grooves about0.5 μm deep are formedin the semiconductor layer 3. Then, 15 passes of blasting are repeatedwhen the average particle size is 8 μm, and 8 passes thereof arerepeated when the average particle size is 13 μm. Thus, the depth of thedividing grooves is increased. Finally, as shown in FIG. 2B, the wholethickness of the semiconductor layer 3 is removed, and further thedividing grooves 7 are formed to reach the depth of about 5 μm in thesubstrate 2. When the dividing grooves 7 with the pitch of 350 μm areformed in the semiconductor wafer 1 about 2 inches square as in thisembodiment, the time required for one pass is about 1 minute.Accordingly, the whole blasting can be terminated in about 15 minutes inthe case of 15 passes. The whole blasting can be terminated in about 8minutes in the case of 8 passes.

Incidentally, the blast-resistant mask 5 is also consumed little bylittle in this blasting. Particularly the whole thickness of each squareplanar corner portion is apt to be worn. Thus, as shown in FIG. 1B, evenin the semiconductor layer 3 protected by the blast-resistant mask 5, asmall radius is apt to be provided in each corner portion thereof.

(3) The blast-resistant mask 5 is removed chemically as shown in FIG.2C.

(4) The surface of the 350 μm-thick substrate 2 in which thesemiconductor layer is not formed is ground by a grinder so that thesubstrate 2 is thinned to be about 100 μm thick uniformly as shown inFIG. 3A.

(5) Scribe lines 8 are formed in the groove bottoms of the dividinggrooves 7 by scribing with a scribing blade as shown in FIG. 1B and FIG.3B.

(6) As shown in FIG. 3C, the semiconductor wafer 1 is divided into alarge number of semiconductor chips 10 by breaking with the scribe lines8 as starting points and along the scribe lines 8.

According to the chip-dividing method of this embodiment, the followingeffects can be obtained.

-   1) When the dividing grooves 7 are formed by blasting, cracking or    chipping that might occur by dicing does not occur in the substrate    2 or the semiconductor layer 3. In addition, the semiconductor layer    3 which might suffer damage by etching does not suffer any damage.    Accordingly, the yield is excellent. For example, the yield is    improved by 10% or more in comparison with that by dicing.-   2) Since a plurality of dividing grooves 7 can be formed    simultaneously by blasting, all the dividing grooves 7 can be formed    in a short time of 8-15 minutes in the semiconductor wafer 1    according to this embodiment as described previously. It would take    about 120 minutes to carry out this, for example, by dicing.    Accordingly, the machining time is shortened on a large scale so    that the efficiency is enhanced.-   3) The blasting machine or the fine particle blast material 21    (particularly silicon carbide) is inexpensive compared with an    etching machine. In addition, the fine particle blast material 21    can be circulated and used repeatedly. It is therefore possible to    reduce the equipment cost and the machining cost.

A group of Examples 1 shown schematically in FIG. 4A to FIG. 4C are topack examples where the dividing grooves 7 are formed by blasting in thesurface of the semiconductor wafer 1 in which the semiconductor layer isformed.

Example 1-1 shown in FIG. 4A is an example corresponding to theaforementioned first embodiment.

Example 1-2 shown in FIG. 4B is an example in which the dividing grooves7 are formed in the surface of the semiconductor wafer 1 in which thesemiconductor layer is formed, and then, a smooth surface newlyappearing by polishing the substrate 2 on the side where thesemiconductor layer is not formed is scribed to form the scribe lines 8.

Example 1-3 shown in FIG. 4C is an example in which a smooth surfacenewly appearing by polishing the substrate 2 on the side where thesemiconductor layer is not formed is scribed to form the scribe lines 8in addition to the aforementioned first embodiment.

A group of Examples 2 shown schematically in FIG. 4D to FIG. 4F are topack examples where the dividing grooves 7 are formed by blasting in thesurface of the semiconductor wafer 1 in which the semiconductor layer isnot formed.

Example 1-1 shown in FIG. 4D is an example in which the dividing grooves7 are formed by the aforementioned blasting in the surface of the about100 μm-thick substrate 2 in which the semiconductor layer is not formed,and then the scribe lines 8 are formed in the groove bottoms of thedividing grooves 7.

Example 2-2 shown in FIG. 4E is an example in which the dividing grooves7 are formed by the aforementioned blasting in the surface of the about100 μm-thick substrate 2 in which the semiconductor layer is not formed,and then, the scribe lines 8 are formed on the side where thesemiconductor layer is formed.

Example 2-3 shown in FIG. 4F is an example in which the dividing grooves7 are formed by the aforementioned blasting in the surface of the about100 μm-thick substrate 2 in which the semiconductor layer is not formed,and then, the scribe lines 8 are formed in the groove bottoms of thedividing grooves 7, while the scribe lines 8 are formed on the sidewhere the semiconductor layer is formed.

In each of Examples, the semiconductor wafer 1 is divided into a largenumber of semiconductor chips by breaking with the scribe lines 8 asstarting points.

Incidentally, the present invention is not limited to the aforementionedembodiment. For example, the dividing grooves 7 may be formed to be deep(for example, 50 μm or more deep in the substrate 2) so that breakingcan be achieved even without scribing.

Next, FIGS. 5 and 6 show a method for dividing a semiconductor waferinto chips according to a second embodiment of the present invention. Asshown in FIG. 5A, a semiconductor wafer 1 to be divided has a basicconfiguration equivalent to that of the semiconductor wafer 1 shown inFIG. 1A and FIG. 1B. That is, the semiconductor wafer 1 is constitutedby a substrate 2 and a semiconductor layer 3. The semiconductor layer 3is formed on the surface of the substrate 2 so as to arrange a lightemitting device (a light emitting diode, a laser diode, or the like).The same layer 3 is constituted by main layers 11 to 16 and electrodes(not shown). The substrate 2 and the main layers 11 to 16 may be madeequivalent to those of the semiconductor wafer 1 shown in FIG. 1A andFIG. 1B.

FIG. 6 shows the second embodiment of the method for dividing theaforementioned semiconductor wafer 1 into chips, which is carried out inthe following steps.

(1) As shown in FIG. 5B and FIG. 6A, first dividing grooves 25 whosegroove width W1 is, for example, about 25 μm are formed by dicing,etching or blasting in the surface of the semiconductor wafer 1 in whichthe semiconductor layer is formed. Each semiconductor chip to be dividedis about 350 μm square in the planar shape. Accordingly, the firstdividing grooves 25 are formed in a planar grid-like arrangement withthe pitch of 350 μm. In addition, as for the depth of the first dividinggrooves 25, the whole thickness of the semiconductor layer 3 is removed,and further the first dividing grooves 25 are formed to reach, forexample, the depth of about 15 μm in the substrate 2.(2) As shown in FIG. 6B, the surface of the 350 μm-thick substrate 2 inwhich the semiconductor layer is not formed is ground by a grinder sothat the substrate 2 is thinned to be about 100 μm thick uniformly.(3) As shown in FIG. 5B and FIG. 6C, second dividing grooves 26 whosegroove width W2 is, for example, about 50 μm are formed by dicing in thesurface of the semiconductor wafer 1 in which the semiconductor layer isnot formed, and in positions corresponding to the aforementioned firstdividing grooves 25. Although it will go well if the first dividinggrooves 25 and the second dividing grooves 26 overlap each otherpartially in their groove widths, it is preferable that the firstdividing grooves 25 stay within the range of the groove width of thesecond dividing grooves 26. It is more preferable that the centralportions of those grooves in their groove width directions substantiallyagree with each other vertically. The second dividing grooves 26 areabout 45 μm deep by way of example. Accordingly, residual portions 2 aof the substrate 2 remaining between the first dividing grooves 25 andthe second dividing grooves 26 are about 40 μm thick.(4) As shown in FIG. 6D, the semiconductor wafer 1 is divided into alarge number of semiconductor chips 10 by breaking in the residualportions 2 a of the substrate 2.

According to the chip-dividing method of this embodiment, the followingeffects can be obtained.

-   1) The groove width W1 of the first dividing grooves 25 formed on    the side of the substrate 2 where the semiconductor layer is formed    is narrower than the groove width W2 of the second dividing grooves    26 formed on the side where the semiconductor layer is not formed.    Accordingly, the area of the semiconductor layer 3 in each    semiconductor chip 10 to be divided is increased so that the    luminance can be enhanced. When the area is not increased, the    number of semiconductor chips 10 yielded can be increased.-   2) The groove width W2 of the second dividing grooves 26 formed on    the side of the substrate 2 where the semiconductor layer is not    formed is made larger than the groove width W1 of the first dividing    grooves 25 formed on the side where the semiconductor layer is    formed. Accordingly, a thick rotary blade having a tendency to have    a long lifetime can be used as the rotary blade of the dicer for    forming the second dividing grooves 26. As a result, the depth of    the second dividing grooves 26 can be increased to thin the residual    portions 2 a and thereby facilitate breaking. In addition, the    exchange cycle of the rotary blade becomes long so that the labor of    exchange can be reduced, and the rotary blade cost can be also    reduced.

A chip-dividing method according to a third embodiment shown in FIG. 7Ais different from that according to the second embodiment only in thatthe following step is added to the second embodiment. That is, after theformation of the second dividing grooves 26 and before the breaking,third dividing grooves 27 are formed by dicing in the groove bottoms ofthe second dividing grooves 26 so as to establish the relationship thatthe groove width of the first dividing grooves 25 is not larger than thegroove width of the third dividing grooves 27, and the groove width ofthe third dividing groove 27 is smaller than the groove width of thesecond dividing grooves 26. The groove width W3 of the third dividinggrooves 27 in the illustrated example is about 25 μm (substantially aswide as the groove width W1 of the first dividing grooves 25), and thedepth is, for example, about 20 μm from the groove bottoms of the seconddividing grooves 26. Accordingly, the residual portions 2 a of thesubstrate 2 become about 20 μm thick.

According to the third embodiment, the residual portions 2 a of thesubstrate 2 become thinner. Accordingly, there can be obtained an effectthat breaking can be facilitated more greatly, while cracks generated atthe time of breaking stay within the groove width range of the thirddividing grooves 27 (narrower than the groove width of the seconddividing grooves 26) so that there is no case that the cracks runextremely obliquely.

A chip-dividing method according to a fourth embodiment shown in FIG. 7Bis different from that according to the second embodiment in thefollowing point. That is, when the second dividing grooves 26 are formedin the second embodiment, the groove sectional shape of the seconddividing grooves 26 is made a substantially U-shape which is the deepestin the widthwise central portion thereof. In the same manner, achip-dividing method according to a fifth embodiment shown in FIG. 7C isdifferent from that according to the second embodiment in the followingpoint. That is, the groove sectional shape of the second dividinggrooves 26 is made a substantially V-shape which is the deepest in thewidthwise central portion thereof.

According to the fourth or fifth embodiment, the residual portions 2 aof the substrate 2 become the thinnest in the widthwise central portionsof the second dividing grooves 26. Accordingly, there can be obtained aneffect that cracking at the time of breaking is apt to occur in thecentral portions in question.

Further, FIG. 8A to FIG. 8C shows modifications of the aforementionedthird to fifth embodiments. In these modifications, when the seconddividing grooves 26 or the third dividing grooves 27 are formed, dicingis performed so that the second dividing grooves 26 or the thirddividing grooves 27 reach the first dividing grooves. As a result, theaforementioned residual portions are not produced, but the semiconductorwafer can be divided directly into semiconductor chips. That is, thestep of dividing the semiconductor wafer into the semiconductor chips bybreaking with the residual portions as starting points can be omitted.Such dicing of the second dividing grooves 26 can be also applied to thechip-dividing method according to the second embodiment as shown by thedotted lines in FIG. 6C. In this case, the step of FIG. 6D isdispensable.

Incidentally, the present invention is not limited to the aforementionedembodiments. The semiconductor chips are not limited to light emittingdevices, but may be formed as electronic devices such as light receivingdevices, FETs, etc.

Further, the present invention is not limited to the aforementionedembodiments, but suitable modifications can be made specifically withoutdeparting from the gist of the invention.

INDUSTRIAL APPLICABILITY

As described above in detail, a method for dividing a semiconductorwafer into chips according to the present invention has the followingexcellent effects. That is, damage to a semiconductor layer is reducedso that the yield can be increased. In addition, the machining time isshortened so that the efficiency can be enhanced. Further, the equipmentcost and the machining cost can be reduced.

Further, the method for dividing a semiconductor wafer into chipsaccording to the present invention has the following excellent effects.That is, the area of the semiconductor layer in each semiconductor chipdivided is increased so that the luminance can be enhanced or the numberof semiconductor chips yielded can be increased, while breaking can bealso facilitated.

1. A method for dividing a semiconductor wafer into a, saidsemiconductor wafer having a semiconductor layer formed on a substrate,comprising: forming a blast-resistant mask on a surface of saidsemiconductor wafer, said blast-resistant mask having a pattern forleaving an exposed portion of said semiconductor wafer; blasting a fineparticle blast material to said semiconductor wafer to thereby formdividing grooves reaching a predetermined depth of said substrate insaid exposed portion; and forming scribe lines by scribing in at leastone of a bottom of said dividing grooves and in a surface of saidsemiconductor wafer opposite to said dividing grooves.
 2. A method fordividing a semiconductor wafer according to claim 1, wherein saidblasting comprises blasting said particle blast material so as to spreadsaid fine particle blast material over a plurality of grid lines of saidexposed portion while feeding said semiconductor wafer and a nozzle forblasting said particle blast material relatively to each other in aplane direction of said semiconductor wafer, such that a plurality ofdividing grooves can be formed.
 3. A method for dividing a semiconductorwafer according to claim 2, wherein a distance between saidsemiconductor wafer and said nozzle is from 10 μm to 150 μm.
 4. A methodfor dividing a semiconductor wafer according to claim 2, wherein a speedof said feeding is from 5 mm/sec to 200 mm/sec.
 5. A method for dividinga semiconductor wafer according to claim 2, wherein said blasting whilefeeding is repeated a predetermined pass number of times to increase adepth of said dividing grooves.
 6. A method for dividing a semiconductorwafer according to claim 5, wherein said pass number of times is 3passes to 20 passes.
 7. A method for dividing a semiconductor waferaccording to claim 1, wherein a width of said dividing grooves is from10 μm to 500 μm.
 8. A method for dividing a semiconductor waferaccording to claim 1, wherein a depth of said dividing grooves in saidsubstrate is from 1 μm to 100 μm.
 9. A method for dividing asemiconductor wafer according to claim 1, wherein said substratecomprises a high hardness material having a Mohs hardness of at least 8.10. A method for dividing a semiconductor wafer according to claim 1,wherein said substrate comprises at least one of sapphire and GaN, andsaid semiconductor layer comprises a gallium-nitride-based compoundsemiconductor.
 11. A method for dividing a semiconductor wafer accordingto claim 1, wherein said particle blast material comprises a materialhaving a Vickers hardness of at least
 120. 12. A method for dividing asemiconductor wafer according to claim 1, wherein said particle blastmaterial comprises at least one of alumina, silicon carbide, boronnitride, boron carbide and diamond.
 13. A method for dividing asemiconductor wafer according to claim 1, wherein said dividing groovesare formed in a surface of said semiconductor wafer in which saidsemiconductor layer is formed.
 14. A method for dividing a semiconductorwafer according to claim 1, wherein said dividing grooves are formed ina surface of said semiconductor wafer in which said semiconductor layeris not formed.
 15. A method for dividing a semiconductor wafer accordingto claim 1, further comprising: dividing said semiconductor wafer intosemiconductor chips by breaking with said scribe lines as startingpoints.
 16. A method for dividing a semiconductor wafer according toclaim 1, wherein said blast-resistant mask comprises a pattern forleaving a grid-like exposed portion.